Compiler Directives

Introduction:

SystemVerilog enhances the capabilities of the ‘define compiler directive to support the construction of string literals and identifiers.

SystemVerilog enhances the capabilities to support standard include specification, and enhances the `include directive to accept a file name constructed with a macro.

‘define macros:

The macro text in SystemVerilog includes

• » \ at the end of a line to show continuation on the next line.
• » ‘ “ overrides the usual lexical meaning of ", and indicates that the expansion should include an actual quotation mark.
• » ‘ \ ‘ “ indicates that the expansion should include the escape sequence \".
• » ‘ ‘ delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments

Example:
`define content(x,y) `"x: `\`"y`\`"`"
This expands:
$display(`content(a1 , a2));
to:
$display("a1: \"a2\"");

‘include

The syntax of the ‘include compiler directive is:

include_compiler_directive ::=
‘include "filename"
Or ‘include

When the filename is the absolute path, only that filename can be included and only the double quote form of the ‘include can be used. When the angle bracket is used, only the vendor defined location containing files defined by the language standard is searched.