Data Declarations - Type Compatibility

Some SystemVerilog constructs and operations require a certain level of type compatibility for their operands to be legal. There are four levels of type compatibility, formally defined here: Equivalent, Assignment Compatible, Cast Compatible, and Non-Equivalent.

Equivalent Types:

Two data types shall be defined as equivalent data types using the following inductive definition. If the two data types are not defined equivalent using the following definition, then they shall be defined to be non-equivalent.

1) Any built-in type is equivalent to every other occurrence of itself, in every scope.

2) A simple typedef or type parameter override that renames a built-in or user defined type is equivalent to that built-in or user defined type within the scope of the type identifier.

Any built-in type is equivalent to every other occurrence of itself, in every scope. A simple typedef or type parameter override that renames a built-in or user defined type is equivalent to that built-in or user defined type within the scope of the type identifier.

typedef bit node; // ’bit’ and ’node’ are equivalent types.
typedef type1 type2; // ’type1’ and ’type2’ are equivalent types.

Assignment Compatible:

All equivalent types, and all non-equivalent types that have implicit casting rules defined between them are assignment compatible types. For example, all integral types are assignment compatible. Conversion between assignment compatible types can involve loss of data by truncation or rounding.

Cast Compatible:

All assignment compatible types, plus all non-equivalent types that have defined explicit casting rules are cast compatible types. For example, an integral type requires a cast to be assigned to an enum. Explicit casting rules are defined in Section 3 Data Types.

Type Incompatible:

These are all the remaining non-equivalent types that have no defined implicit or explicit casting rules. Class handles and chandles are type incompatible with all other types.