DIGITAL FAQ'S :

Ans : To introduce small delays. To eliminate cross talk caused due to inter electrode capacitance due to close routing, buffers support high fan-out.

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Ans : Digital Signals are easy to store and easy to manipulate without error. Accuracy increases by increasing number of levels. Here cost of the hardware is proportional to accuracy. Where in analog, signal values are stored in capacitors it is not constant for long time it may increase or decrease because of noise. Accuracy increases by increasing more sensible coils. Here the cost of the require hardware is much more to α to accuracy.

Ans : Minimum number of inputs that are necessary to generate a particular next state when the current state is known. Similar to truth table or state table, but rearrange the data so that the current state and next state are next to each other on the L.H.S of the table and the inputs needed to make that state change happened are shown on the R.H.S of the table.

Characteristic Table

Ans : In asynchronous changing state bits are used as clock to subsequent state machines. Synchronous all flip flops gets clock at the same time. All state bits change under the control of single clock.

Ans : Sequence depends on initial pattern. XOR gate can be given at any where.

Ans : To check transmission over a wire for period of time. To Establishing the reliability communication between two points. To test any system.

Ans : The summation of all delays encountered from where the clock occurs to the output. In short, the delays of the State memory (R) and the output logic (G).
PD Clock- Output (min) = Rpd (min) + Gpd (min)
PD Clock- Output (max) = Rpd (max) + Gpd (max)

Ans : This is a property associated with Mealy machines only. The calculation is the summation of all propagation delays encountered between the input and the output.
For MOORE machines:
PD Input- Output (min) = infinity (∞)
PD Input- Output (max) = infinity (∞)
For MEALY Machines:
PD Input- Output (min) = Gpd (min)
PD Input- Output (max) = Gpd (max)

Ans : The calculation for setup time is the sum of the setup time for the concerned flip flop and the maximum delay from the input logic (F).
T SETUP = RSetup+ Fpd (MAX).

Ans : T HOLD = RHold - Fpd (MIN)

Ans : MCLK = 1/ TMIN Calculate TMIN first, TMIN refers to the minimum time period for correct operation of the circuit, it is calculated using all worst cases i.e maximum delays.
TMIN = Fpd (MAX) + RSetup + Rpd (MAX)

Ans : Given two sequentially-adjacent registers, Ri and Rj and an equipotential clock distribution network, the clock skew between these two registers is defined as
Tskew = Tci - Tcj
Here Tci and Tcj are the clock delays from the clock source to the registers Ri and Rj, respectively.

Ans : Clock gating is one of the power-saving techniques used on the Pentium 4 processor. To save power, clock gating refers to activating the clocks in a logic block only when there is work to be done.

Ans : In NAND gates at the transistor level the mobility of electrons is normally three times compared to holes mobility in NOR, thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower.

Ans : The minimum amount of noise that can be allowed on the input stage for which the output won’t effect.

Ans : This will happen if the O/P cap is not allowed to charge/discharge fully to the required logical levels. If there is a setup time violation, metastability will occur, to avoid this, a series of flip-flops is used (normally 2 or 3) which will remove the intermediate states.

Ans : The late coming signals are to be placed closer to the output node i.e, A should be placed closer to the output.

Ans : S(x, y, z) = S (1, 2, 4, 7)
C(x, y, z) = S (3, 5, 6, 7)

Ans : Tie one of xor gates input to 1 it will act as inverter. Tie one of xor gates input to 0 it will act as buffer.

Ans : Bufgds that is differential signaling buffers which are inbuilt resource of most of FPGA can be used.

Ans : Compares A = A3 A2 A1 A0 with B = B3 B2 B1 B0 Output = 1 if A = B

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Ans : Setup violation can be fixed by slow down the clock. But hold time can't be fixed by this way. By inserting buffer in the path we can reduce the hold violations.

Ans : Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge. Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Ans : Enters into metastable state. At the end of metastable state, the flip-flop settles down to either '1' or '0'.

Ans : Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different points(components) at different times.

Ans : Local skew: The difference between the clock reaching at the launching flop v/s the clock reaching the destination flip-flop of a timing-path. Global skew: The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain. Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

Ans : Virtual clock is mainly used to model the I/O timing specification. Based on what clock the input/output pads are passing the data.

Ans : 'Slack' is the amount of time that is measured from when an event 'actually happens' and when it must 'happen'. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually happen'. When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead – Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time.

Ans : Mealy and Moore models are the basic models of state machines.
A state machine which uses only Entry Actions, so that its output depends on the state, is called a Moore model.
A state machine which uses only input actions, so that the output depends on the state and also on inputs, is called a Mealy model.

Ans : Mealy machine has outputs that depend on the state and input. Moore machine has outputs that depend on only state. In Mealy as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level. The outputs are properties of states themselves. Which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output. Choice of a model depends on the application

Ans : A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely encode the number of states in the state machine. The actual number of flip-flops required is equal to the ceiling of the log-base-2 of the number of states in the FSM. A one-hot FSM design requires a flip-flop for each state in the design and only one flipflop (the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design. For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a one-hot FSM requires a flip-flop for each state in the design.

Ans : SDRAM receives its address command in two address words. It uses a multiplex scheme to save input pins. The first address word is latched into the DRAM chip with the row address strobe. The RAS command is the column address strobe (CAS) for latching the second address word.

Ans : Ex: Consider 0110=6 a left shift will make it 1100=12, multiplied by 2 and right shift will make it 0011=3, right shift will Divide the value by 2.

Ans : RULES: frequency(clk_A) = frequency(clk_B) / 4, period(en_B) = period(clk_A) * 100, duty_cycle(en_B) = 25%
Lets assume clk_B = 100MHz (10ns)
From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for 1000ns,due to (3), so 3000ns of the enable we are doing no output work. Therefore, FIFO size = 3000ns/40ns = 75 entries.

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Ans : At transistor level of a module, active low means the capacitor in the output terminal gets charged or discharged based on low to high and high to low transition respectively. When it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output capacitance to discharge rather than charging.

Ans : Setup time

Ans : D-latch is level sensitive where as flip-flop is edge sensitive. Flip-flops are made up of latches.

Ans : Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line.

Ans : By giving the feedback we can convert, i.e !Q=>S and Q=>R. Hence the S and R inputs will act as J and K respectively.

Ans : By connecting the J input to the K through the inverter.

Ans : A condition in which, the clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0. By using master-slave or edge-triggered flip-flop we can overcome this.

Ans : XOR each bits of A with B and the output of 4 xor gates are then given as input to 4-input nor gate. If output is 1 then A=B.

Ans : 6 clock cycles

Ans : Connect Qbar to D and apply the clock at clock of DFF and take the O/P at Q.

Ans : Max. Freq of operation is given by 1/ (propagation delay+setup time) = 1/16ns = 62.5 Mhz

Ans : If N=Odd, the circuit acts as even parity detector. If N=Even, just the opposite, it will be Odd parity detector.

Ans : All the bits of subtrahend should be connected to the xor gate. Other input to the xor being one. The input carry bit to the full adder should be made 1. Then the full adder works like a full subtracter.

Ans : Setup violations are related to two edges of clock, we can vary the clock frequency to correct setup violation. But for hold time, we only concerned with one edge and not basically depend on clock frequency.

Ans : 2(power n)-2n is used to find the unused states in Johnson counter. For 3-bit counter it is 8-6=2 unused states.

Ans : LFSR is a linear feedback shift register where the input bit is driven by a linear function of the overall shift register value.

Ans : False path is defined as, the paths in the circuit which are never exercised during normal circuit operation for any set of inputs. Static Timing Analysis tools are able to identify simple false paths. However they are not able to identify all the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its timing performance predictable.

Ans : Clock skew of 60ps is more likely to have clock power. Because it is likely that low-skew processor has better designed clock tree with more powerful and number of buffers and overheads to make skew better.

Ans : Multi-cycle paths are paths between registers that takes more than one clock cycle to become stable. Place and Route tools are capable of fixing multi-cycle paths problem.

Ans : The synchronous counter will have lesser delay as the input to each flop is readily available before the clock edge. Eg: 16 state counter = 4 bit counter = 4 Flip flops Let 15ns be the delay of each flop.
The worst case delay of ripple counter = 15 * 4 = 60ns
The delay of synchronous counter = 15ns

Ans : FIFO does not have address lines Ram is used for storage purpose where as fifo is used for synchronization purpose.

Ans : Two sensors are required to find out the direction of rotating. One of them is connected to the data input of D flip-flop and second one to the clock input. If the circle rotates the way clock sensor sees the light first while D input (second sensor) is zero - the output of the flip-flop equals zero and if D input sensor "fires" first - the output of the flip-flop becomes high.

Ans : The waveforms are shown in the following figure.

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Ans : It is always n-1, where n is number of inputs. So 16 input parity generator will require 15 two input xor's.

Ans : 9's compliment is nothing but subtracting the given no from 9. So using a 4 bit binary adder we can just subtract the given binary no from 1001 here we can use the 2's compliment method addition.

Ans : Write-back caching method in which modifications to data in the cache are not copied to the cache source until absolutely necessary. Write-through cache performs all write operations in parallel, data is written to main memory and the L1 cache simultaneously. Write-back caching yields somewhat better performance than write-through caching because it reduces the number of write operations to main memory. A write-back cache is also called a copy-back cache.

Ans : Asynchronous systems do not send separate information to indicate the encoding or clocking information. The receiver must decide the clocking of the signal on it’s own. This means that the receiver must decide where to look in the signal stream to find ones and zeros, and decide for itself where each individual bit stops and starts. Synchronous systems negotiate the connection at the data-link level before communication begins. Basic synchronous systems will synchronize two clocks before transmission, and reset their numeric counters for errors etc. More advanced systems may negotiate things like error correction and compression. It refers to processes where data must be delivered within certain time constraints.