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Chapter 5-10
Chapter 10-15
Chapter 15-20
Chapter 20-25
Chapter 25-30
Latched Logic
SystemVerilog also provides a special always_latch procedure for modeling latched logic behavior. For example:
always_latch
if(ck) q <= d;
The always_latch procedure determines its sensitivity and executes identically to the always_comb procedure.
Software tools can perform additional checks to warn if the behavior within an always_latch procedure does not represent latched logic.