Parameters

Verilog-2001 provides three constructs for defining compile time constants: the parameter, localparam and specparam statements. A module, interface, program or class can have parameters, which are set during elaboration and are constant during simulation. They are defined with data types and default values. With SystemVerilog, if no data type is supplied, parameters default to type logic of arbitrary size for Verilog-2001 compatibility and interoperability.

SystemVerilog adds the ability for local parameters to be declared in a generate block. Local parameters can also be declared in a package or in a compilation unit scope. In these contexts, the parameter keyword can be used as a synonym for the localparam keyword.

$ associated with parameters in SystemVerilog can be used in different ways:

a) $ can be assigned to parameters of integer types. A parameter to which $ is assigned shall only be used wherever $ can be specified as a literal constant.

Ex: parameter p1 = $;

This p1 parameter represents an unbounded range specification.

b) A system function is provided to test whether a constant is a $. The syntax of the system function is :

$isunbounded (const_expression);

$isunbounded returns true if const_expression is unbounded.

c) $ is used in writing properties concisely where the range is parameterized.

d) A property can be configured according to the requirements by testing for a $

SystemVerilog also adds the ability to omit the parameter keyword in a parameter port list.

Ex: typedef bit#(16) word;