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System Functions - Miscelleneous

Assertion severity system tasks

SystemVerilog assertions have a severity level associated with any assertion failures detected. By default, the severity of an assertion failure is “error”. The severity levels can be specified by including one of the following severity system tasks in the assertion fail statement:

Each of the severity tasks can include optional user-defined information to be reported.

Assertion control system Tasks

SystemVerilog provides three system tasks to control assertions.

$assertoff shall stop the checking of all specified assertions until a subsequent $asserton. An assertion that is already executing, including execution of the pass or fail statement, is not affected

$assertkill shall abort execution of any currently executing specified assertions and then stop the checking of all specified assertions until a subsequent $asserton.

$asserton shall re-enable the execution of all specified assertions

assert_control_task ::=
assert_task [ ( levels [ , list_of_modules_or_assertions ] ) ] ;
assert_task ::=
Or $assertoff
Or $assertkill

Assertion system functions

assert_boolean_functions ::= assert_function ( expression ) ;

Assertions are commonly used to evaluate certain specific characteristics of a design implementation, such as whether a particular signal is “one-hot”. assert_function

Random number system functions

There are three system functions for generating pseudorandom numbers,

1. $urandom:

The syntax for $urandom is:

function int unsigned $urandom [ (int seed ) ] ;

It provides a mechanism for generating pseudorandom numbers. The function returns a unsigned new 32-bit random number each time it is called.

2. $urandom_range

The syntax for $urandom_range() is:

function int unsigned $urandom_range( int unsigned maxval,int unsigned minval = 0 );

3. $srandom

The $urandom_range() function returns an unsigned integer within a specified range. The syntax of the srandom() method is:

function void srandom( int seed );

The s srandom() method allows manually seeding the Random Number Generator (RNG) of objects or threads.

Program control:

» Each program can be explicitly exited by calling the $exit system task.

» When all programs exit (implicitly or explicitly), the simulation finishes and an implicit call to $finish is made.

» Syntax : task $exit();

Coverage system functions:

SystemVerilog has several built-in system functions for obtaining test coverage information:

$coverage_control : This function is used to control or query coverage availability in the specified portion of the hierarchy.

$coverage_get_max : This function obtains the value representing 100% coverage for the specified coverage type over the specified portion of the hierarchy. This value shall remain constant across the duration of the simulation

$coverage_get : This function obtains the current coverage value for the given coverage type over the given portion of the hierarchy.This number can be converted to a coverage percentage

$coverage_merge : This function loads and merges coverage data for the specified coverage into the simulator. name is an arbitrary string used by the tool, in an implementation-specific way.

$coverage_save : This function saves the current state of coverage to the tool’s coverage database and associates it with the given name.

Enhancements to Verilog-2001 system tasks

SystemVerilog extends the behavior of the following:

$readmemb and $readmemh

$readmemb and $readmemh are extended to unpacked arrays of packed data but not defined for packed arrays or unpacked arrays of unpacked data. Associative arrays of packed data, and dynamic arrays of packed data. The system tasks treat each packed element as the vector equivalent and perform the normal operation.

$writememb and $writememh

$writememb and $writememh are used to dump memory contents to files that are readable by $readmemb and $readmemh, respectively. If “file_name” exists at the time $writememb or $writememh is called, the file will be overwritten.