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Tasks & Functions - Introduction

Verilog-2001 has static and automatic tasks and functions. Static tasks and functions share the same storage space for all calls to the tasks or function within a module instance. Automatic tasks and function allocate unique, stacked storage for each instance.

SystemVerilog adds the ability to declare automatic variables within static tasks and functions, and static variables within automatic tasks and functions. SystemVerilog also adds:

» More capabilities for declaring task and function ports
» Function output and inout ports
» Void functions
» Multiple statements in a task or function without requiring a begin...end or fork...join block
» Returning from a task or function before reaching the end of the task or function
» Passing arguments by reference instead of by value
» Passing argument values by name instead of by position