VERILOG FAQ'S :

Ans :The situation when two expressions are allowed to execute at same instance of time without mentioning the order of execution.

Ans : 1. Behavioral level 2. Register-Transfer level 3. Gate level 4. Switch levels

Ans : Top down and Bottom up

Ans : 8'bxxxx_xxxx

Ans : Wire just transfer input to output, Register stores the value as a variable until or unless another value replaces it.

Ans : Reduction and takes one operand and perform a bit by next bit operation.

Ans : We use temp register in case of blocking statements to swap the registers contents. We wont use temp register for non blocking          statements.

Ans : In logical shift the MSB will be accumulated by zero's In arithmetic shift MSB will be accumulated by sign bit.

Ans : Operator which assigns any one variable out of two by evaluating the expression mentioned in that operator. Syntax : cond_expr?          true_expr:false_expr

Ans : “==” it is logical equality.
         “===” it is case equality.

Ans : Reg can hold up to 13 characters.

Ans : b

Ans : gates, transmission gates and switches.

Ans : Port order connection and Port name connection.

Ans : A continuous assignment statement.

Ans :The rise delay is associated with a gate output transition to 1 from another value(0,x,z).
         Turn off delay associated with a gate transition to Z from value (0,1,x).

Ans : Delay where command waits for particular time steps before executing that command.
         ex: #10 a=b+c;

Ans : Here the evaluated expression waits for specified time to assign value to LHS.
         ex : a = #10 b+c;

Ans : Inter delay simply wait for appropriate no of time steps before executing the command.
         ex : #10 q = x + y;
         Intra delay wait for appropriate no of time steps before assignment of RHS to LHS.
         ex : q = #10 x + y;

Ans : b

Ans : Difference between continuous and procedural assignments.
         Continuous assignments procedural assignments
         1 Assigns primarily to net Assigns primarily to reg
         2 Values continuously drive to out put Values will be stored into variables
         3 Occurs in assignments to wire,port and net Occurs in constructs like always,initial,task,function.

Ans : Assignment in initial Assignment in always
         1. Execute from time 0 in simulation and proceed in the specified sequence. This also begin from time 0, and repeat forever as a function            of the changes on sensitivity list.
         2. Execution stops when the end of the block is reached. Execution continuously repeats according to the change in values of sensitivity            list.
         3. Non-synthasizable Synthasizable

Ans : Blocking Non blocking
         1. The evaluation of the expression of the RHS is updated to LHS autonomously based on delay. But here RHS will not be updated to LHS            immediately
         2. In case of multiple blocking assignments the trailing assignments are blocked. Multiple blocking assignments can be scheduled to occur            concurrently on next evaluation cycle.
         3. There is a possibility of race condition in this. Race condition can be avoided.
         4 Represented by “=” operator sign between LHS and RHS. Represented by “< =”operator sign between LHS and RHS.

Ans : Task Function
         1. Can contain time control statements like @(posedge). Executes in zero simulation time.
         2. Can call any number of function or tasks. Can call any number of functions but not tasks.
         3. Cannot return any value when called instead the task can have output arguments. It can return any value when called.

Ans : Re-entrant task,functions have a key word automatic between task and name of the task which replicates and allocates the variables. But          it is not possible in static.

Ans : By adding key word automatic between task and name of the task.

Ans : It replicates the variables and allocates the variables in task.

Ans : fork--join groups two or more statements together in parallel, so that all statements are evaluated concurrently.

Ans : Procedural assignment statements.

Ans : Procedural

Ans : It is an event timing control that controls when all statements in the procedural block will start to be evaluated.

Ans : The statements within a procedure which executes sequentially.

Ans : By using non blocking statements.

Ans : Blocking can be represented by wire.
         Non blocking can be represented by latch.

Ans : event, fork and join, disable.

Ans : It suspends the process until specified event to occur.

Ans : It suspends the process until expression become true.

Ans : this loop executes continuously and never completes until you break it intentionally.

Ans : Generate statements are used when the same operation or module instance is repeated for multiple bits of vector.

Ans : Generate loop, Generate conditional, Generate case.

Ans : 1. Combinational UDP
         2. Sequential UDP

Ans : It is important to improve designers productivity to meet today's design complexity.

Ans : The only difference is always with @ can be synthesized but not other one.
         The always without @ will be used only in test benches.

Ans : $display display its parameter whenever that is executed. $monitor display its parameter whenever the value of parameter changes.

Ans : assign mux_out = (sel)? din_1 : din_0;

Ans : always @ (posedge clk_in)
if (reset)
clk_out <= 1'b0;
else
clk_out <= ! clk_out ;

Ans : assign out = { binary[3]),(binary[3] ^ binary[2]), (binary[2] ^
binary[1]),(binary[1] ^ binary[0]) };

Ans : always @ (posedge clk)
if (reset)
out <= 8'b0000_0001 ;
else if (enable)
out <= {out[6],out[5],out[4],out[3],
out[2],out[1],out[0],out[7]};

Ans : always @(posedge clk)
if (reset)
out <= 16'b0 ;
else if (enable)
out <= out + 1;

Ans : assign parity_out = ^data_in; // data_in is 8 bits

Ans : always @(posedge Clock)
begin
register <= register << 1;
register[0] <= Input;
end
assign output = register[7];

Ans : assign {Carry_Out,SUM} = input_A + input_B + Carry_In;

Ans : assign out = (in_1 >= in_2)? 1'b1:1'b0;

Ans : FSMs are widely used in applications that require prescribed sequential activity.

Ans : Define Parameter only one constant with the same name can exist in the whole scope multiple modules can have same parameter name cannot be overridden can be overridden used to specify macro used to specify constants

Ans : When there are multiple nonblocking assignments made to the same reg variable in a sequential always block, then the last assignment is picked up for logic synthesis.

Ans : A snake path, as the name suggests is a path that traverses through a number of hierarchies, and may eventually return back to the same hierarchy from which it originated.

Ans : Constant propagation is a very effective technique for area minimization, since it forces the synthesis tools to optimize the logic in both forward and backward directions. Since the area minimization is achieved using constants, this technique is called constant propagation.

Ans : When any of the bits of a reg declaration is unused, the logic corresponding to those bits gets optimized

Ans : Both `ifdef and generate constructs can be used for the purpose of area minimization.

Ans : `ifdef generate we can use it inside the module as well as outside the module we can only use it inside the module works on the boolean presence or absence of `define of the `ifdef variable use the value of a variable using genvar, can be used inside loops used only in if-else and cannot perform any looping operation the genvar variable can be used inside for loop or case statements

Ans : Retiming is the process of relocating registers across logic gates, without affecting the underlying combinatorial logic structure. This process is achieved by borrowing logic from one time frame and lending it to the other, while maintaining the design behavior.

Ans : Since there is one explicit FF per stage of a one-hot encoded state machine, there is no need of output state decoding. Hence, the only anticipated delay is the clock to q delay of the FF. This makes the one-hot encoding mechanism preferable for high-speed operation.

Ans : Reset of a FF driven by the output of another FF Presence of tri-state buses in the design Presence of derived clocks in the design Presence of gated clocks in the design Presence of latches in the design

Ans : Reduce switching of the data input to the Flip-Flops. Reduce the clock switching of the Flip-Flops. Have area reduction techniques within the chip, since the number of gates/Flip-Flops that toggle can be reduced.

Ans : It is easy to debug the internal signals of a design, especially if they are not a part of the top level pinout.

Ans : During synthesis, these hierarchical names get ungrouped or dissolved or renamed, depending upon the synthesis strategy and switches used, and hence, will cease to exist. In that case, special switches need to be added to the synthesis compiler commands, in order to maintain the hierarchical naming. If the Verilog code needs to be translated into VHDL, the hierarchical names are not translatable.

Ans : Specifying any kind of delay before an assignment, or within an assignment, in a blocking or non-blocking procedural assignment is ignored by synthesis tools. If the functionality depends upon the presence of the delay, then a mismatch in functional simulation will be seen between the model and the synthesized netlist. Ex: reg1 = #3 reg2; // #3 will be ignored #6 reg3 <= reg4; // #6 will be ignored Since the above construct is syntactically legal, the synthesis tools will issue a WARNING and not an ERROR.

Ans: 8:1 Mux

Ans: 2:4 Decoder

Ans : Completely specify all branches for every case and if statement. Completely specify all outputs for every case and if statement. Use synopsys full-case if all desired cases have specified.

Ans : A "full" case statement is a case statement in which all possible case-expression binary patterns can be matched to a case item or to a case default. If case statement does not include a case default and if it is possible to find a binary case expression that does not match any of the defined case items, the case statement is not full.

Ans : A parallel case statement is a case statement in which it is only possible to match a case expression to one and only one case item. If it is possible to find a case expression that would match more than one case item, the matching case items are called "overlapping" case items and the case statement is not parallel.

Ans : Latch takes less area, consume less power, facilitate time borrowing or cycle stealing, not friendly with DFT tools
always @(clk) begin
IF (clk == 1’b1)
q <= d;
end
Flip-flop takes more area, consumes more power, allow synchronous logic, friendly with DFT tools.
D-Flip-flop:
always @(posedge clk)
begin
if(reset)
q<=1'b0;
else
q <= d;
end

Ans : D type flip flop with synchronous reset
reg q;
always @ (posedge clk)
if (reset)
q <= 1'b0;
else
q <= d;

Ans : D type flip flop with asynchronous reset
reg q;
always @ (posedge clk or posedge reset)
if (reset)
q <= 1'b0;
else
q <= d;

Ans : D type flip flop with gated clock
reg q;
wire gtd_clk = enable && clk;
always @ (posedge gtd_clk)
q <= d;

Ans : Non-parallel case statements infer priority encoders. It is a poor coding practice to code priority encoders using case statements. It is better to code priority encoders using if-else-if statements.
Code all intentional priority encoders using if-else-if statements. It is easier for a typical design engineer to recognize a priority encoder when it is coded as an if-else-if statement.
Case statements can be used to create tabular coded parallel logic. Coding with case statements is recommended when a truth-table-like structure makes the Verilog code more concise and readable.
Examine all synthesis tool case-statement reports.
Change the case statement code, as outlined in the above coding guidelines, whenever the synthesis tool reports that the case statement is not parallel (whenever the synthesis tool reports "no" for "parallel_case").

Ans : The presence of internal tri-state logic is a critical consideration for power sensitive products. Normally a multiplexer should be used in place of tri-state logic. However, if the tri-state logic remains in the RTL, it is not an error for compilation. Synthesis tools sometimes warn the users. The linting tools also detect this condition, and report this to the user.

Ans : If a range is not specified, Verilog will assume a 1 bit return value. If a multi-bit return value was calculated in the function, only the least significant bit is returned.

Ans : $monitor can be selectively enabled or disabled by the $monitoron and the $monitoroff system calls, respectively. The $monitoron and $monitoroff system calls affect only the most recent call to $monitor.

Ans : The main limitation of fork-join construct in Verilog is that it is static, that is, the execution of the code beyond the join is suspended until all the processes within the fork-join are completed.

Ans : The logical shift operators are (<< and >>). The logical shift operator has been present from Verilog-1995. The arithmetic shift operators are (<<< and >>>), which were introduced with Verilog-2001. Three of them, that is, logical left shift (<<), arithmetic left shift (<<<) and logical shift right(>>) operators, shift the bits left/right by the number of bit positions specified by the right operand, and the vacated bits are filled with zeros. The arithmetic right shift operator (>>>) will fill the vacated bits with 0 if the left operand is unsigned, and the most significant bit if the left operand is signed.

Ans : The “==” are synthesizable while “===” operators are not synthesizable.

Ans : Force - release can be applicable to nets and variables, whereas assign - deassign is applicable only to variables.

Ans : There can be more than one critical path in a design. A critical path is the path through a circuit that has the least slack. Need not necessarily the longest path in the design.

Ans : A module with only inputs and no outputs will synthesize into a module with no logic, since there is nothing to be synthesized as an output.

Ans : Casex – treats x,z both as don’t cares.

Ans : module ring_counter(clk, initial_count, count);
input clk, initial_count;
output reg [7:0] count;
always @ (posedge clk)
begin
if (initial_count)
count = 8’b00000000;
else
count = {count (6:0), count[7]};
endmodule

Ans : It is compiler directive which indicates the time unit to be used for delays specified in the testbench.

Ans : Event-based Simulator:
Event base Simulation method sacrifices performance for rich functionality.
Every active signal is calculated for every device it propagates through during a clock cycle.
Full timing calculations for all devices and the full HDL standard.
Cycle Based Simulator:
Cycle based Simulation method eliminates unnecessary calculations to achieve huge performance gains in verifying Boolean logic.
At the end of every clock cycle results are examined.
The digital logic is the only part of the design simulated. These simulators are mainly meant for logic verification, no timing calculations. By limiting these calculations, cycle based Simulators can provide huge increases in performance over Event-based simulators.
Static Timing analysis is used to compensate for the lost timing information coverage.

Ans : The width elements of ports, wire or reg declarations require a constant in both MSB and LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value of these widths. For example, the following code is erroneous before Verilog 2001 version. reg [ port1(val1:vla2) : port2 (val3:val4)] reg1; Verilog-2001 allows the use of a function call to evaluate the MSB or LSB of a width declaration.

Ans : System Verilog has introduced a keyword alias, which can be used only on nets to have a two-way assignment.
module top_alias ();
wire rhs,lhs;
alias lhs=rhs;
In the above verilog code, if LHS changes it reflets to RHS and similarly if RHS changes it reflects to LHS as well.

Ans :The operator (?) gives answers even if the condition is "x", so for example if con = 1'bx, a = 'b10, and b = 'b11, it will give c = 'b1x. Whereas “if” treats Xs or Zs as FALSE, so it will return always c = b.

Ans : Verilog basically imply a four-level deep queue for the current simulation time:
Active Events (blocking statements)
Inactive Events (#0 delays, etc)
Non-Blocking Assign Updates (non-blocking statements)
Monitor Events ($display, $monitor, etc).

Ans : Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program.

Ans : $display – Displays once every time when they are executed.
$strobe – Displays the parameters at the very end of the current simulation time rather than exactly where it is executed.
$monitor – Displays every time when one of its parameter changes.
$reset – Resets the simulation back to zero.
$stop – Halts the simulator and puts in the interactive mode where user can enter commands
$finish – Exits simulator back to operating system.
$time, $stime, $realtime – Currenmt simulation time as a 64-bit integer, 32-bit integer and real number respectively.
$scope (hierarchy_name) – sets the current scope to hierarchy scope to hierarchy name.
$showscopes – Lists all modules,tasks & block naems in current scope.
$fopen – Opens an ouput file and gives the open file a handle for use by the other commands.
fclose – Closes the file and lets the other programs access it.
$fdisply, $fwrite – Writes formated data to a file when ever they executed. Both are same except $fdisplay inserts a new line after every execution and $fwrite does not inserts.
$fstrobe – Writes a file when executed, but waits until all other operations in the time step are complete before writing.
initilal
# 1 a= 1; b=0;
#fstrobe (file, a,b );
b=1;
Will writes 11 for a and b.
$fmonitor – Writes to a file when ever any argument changes
$dumpfile, $dumpvar, $dumpon, $dumpoff, $dumpall – The dump files are capable of dumping all the variables in a simulation.
$dumpvar – dumps all the variables in the design.
$dumpvar(1,top) – Dumps all variables in the top and below but not sub modules.
$dumpvar(2,top) – Dumps all variables in the top and one level below.
$dumpvar(n,top) – Dumps all variables in the top and n-1 level below.
$dumpvar(0,top) – Dumps all variables in the top and all levels below.
$dumpon – Initiates the dump.
$dumpoff - Stops dumping.
$random – Generates radom integer every time when it is called.

Ans : Gate level representation of RTL.

Ans : Memories are declared as two-dimensional arrays of registers.
syntax: reg [msb:lsb] identifier [first_addr:last_addr] ;
Where msb:lsb determine the width (word size) of the memory first_addr:last_addr determine the depth (address range) of the memory

Ans : A function cannot advance simulation-time, using constructs like #, @. etc.
A function should not have nonblocking assignments.
A function without a range defaults to a one bit reg for the return value.
It is illegal to declare another object with the same name as the function in the scope where the function is declared.