VHDL FAQ'S :

Ans : VHDL stands for VHSIC Hardware description language. Where VHSIC stands for Very High Speed Integrated Circuit.

Ans : a) std_logic_1164.
b) numeric_std.
c) numeric_bit .
d) std_logic_arith .
e) std_logic_unsigned .

Ans : Simulating sinthesized netlist is called Gate-level simulation.

Ans : The main advantage is that the testbench can be re-used with synthesized circuit that means we can apply similar test patterns to gate level model to verify that it has response similar to original model.

Ans : Implementation tool.

Ans : This can be done by creating timing model by implementation tool. Where the timing model consist of gate-level primitives augmented with detailed delay information and can be used to verify the timing behavior.

Ans : ’U’ --Uninitialized ’X’ --Forcing Unknown ’0’ --Forcing 0 ’1’ --Forcing 1 ’Z’ --High Impedance ’W’ --Weak Unknown ’L’ -- Weak 0 ’H’ -- Weak 1 ’-’ -- don’t care

Ans : No, because floating point numbers cannot be mapped to hardware.

Ans : architecture architecture_name of entity_name architecture_declarative_part; begin Statements; end architecture_name;

Ans : It is that block of code which will bind the perticular architecture body to its entity and a component with an entity.

Ans : configuration configuration_name of entity_name is block_configuration; end configuration_name;

Ans : Block_configuration in configuration block signifies binding of component in a block. The syntax is as shown below for block_name component_binding; end for;

Ans : use.

Ans : Component_label: component_name port map (signal_list);

Ans : We can't instantiate entity/architecture pair directly Instead we can include component declaration in structural architecture body.

Ans : Signal, Variable, Constant.

Ans : Scalar Types and Composite Types

Ans : Array and Record

Ans : Array contain many elements of the same type. But Record contains many elements of different types.

Ans : Alias is an alternative name assigned to part of an object. alias alias_name : subtype is name;

Ans : Subtype is mainly used for range checking and for imposing additional constraints on types.

Ans : subtype subtype_name is base_type range_constraint;

Ans : Signals are like a wires which connect design entities together and communicate changes in values within a design.

Ans : After delta delay

Ans : Type and Type attributes, value, time.

Ans : “ < = “

Ans : Signal assignment is concurrent outside the process and sequential within a process.

Ans : Inertial delay and Transport delay

Ans : using after clause.

Ans : This is the delay often found in switching circuits where spikes will not propogate further in circuit.

Ans : Transport delay models the behavior of a wire, in which all pulses are propagated irrespective there width

Ans : delta delay.

Ans : block statements don't have special functionality as such it separates part of the code without adding any functionality.

Ans : Processes will be executed concurrently but statements within process will be executed sequentaily.

Ans : zero simulation time.

Ans : Combinational and Clocked processes.

Ans : variables are key words used to declare and can be used inside a process or subprograms. Variable assignment occurs immediately. Variable retain their variables throughout the entire simulation. Require less memory Constant are identifiers with a fixed value. They should not be assigned any values by the simulation process.

Ans : Signals Connects design entities together. Signals can be declared both inside and out side of the process. It has three properties like type & type attributes, Value, Time. Signals assign its value after delta delay. Signals require more memory. Variable These are the identifiers within process or subprograms. This can only be declared within process can't be used outside a process. It has only two properties like Type,Value. Variable assigned its value immediately. Variable require less memory.

Ans : if, elsif, else, case, loops,wait statement.

Ans : wait on signal, wait until boolean_expr, wait for time_expr

Ans : Real is not synthesizable.

Ans : library work;
use work.pkg_name.all;
Add these lines in code just after the standard library declaration.

Ans : We need following tools
1. Simulation tool. 2. Synthesis tool. 3. Implementation tool.

Ans : We use a tool called simulator to simulate the model to verify that the description is working as intended.

Ans : Concurrent language and strongly typed language.

Ans : Concurrency.

Ans : By sending different input to design by testbench.

Ans : VHDL allows LHS & RHS operators of same type.
Different types in LHS & RHS is illegal in VHDL

Ans : Data flow level, Structural Level, Behavioral Level

Ans : Concurrent statements will be used in data flow level and Sequential statements will be used in behavioral level.

Ans: Sequential circuit uses flip flops. Sequential circuits have state, which means basically they have memory. They compute the output based on input and the state and updated based on clocks. A combinational circuit does not have any states. They are functions of only inputs but not clocks. They are basically used to implement Boolean function.

Ans: To select one of the many architecture bodies that an entity may have.

Ans: Concurrent statements can be conditionally selected or replicated during the elaboration phase. This is called generate .there are two forms of generate. -for generate -if generate

Ans: These provide access to object that contains a sequence of values of a given type. Values belonging to access type are pointers to a dynamically allocated object of some other type.

Ans: Generics are used to pass certain type of information into o design description from its environment.

Ans: Yes, we can. But the range of variable should be limited such that it doesn’t access outside the array limits.

Ans: It is a collection of values that may belong to different types.

Ans: Latches are level sensitive and flip flops are edge sensitive. Latch allows time borrowing where as flip-flop does not allow time borrowing. Latches hold the last logic at output if we put it off. Flip-flops transfer data only at that instant of time and can be changed until next signal change.

Ans: setup time is the time required for the synchronous inputs of a flip-flop to be stable before a clock pulse is applied. Hold time is the time that the synchronous inputs of a flip-flop remain stable after the active clock transaction is finished.

Ans: Metastability is an unknown state. It is neither 0 or nor 1. If the setup time and hold time are violated, the flip-flop goes into metastability state.

Ans: 1. Using proper synchronizers. 2. Using faster flip-flops.

Ans: An attribute is a value, function, range, signal, type or constant that can be associated with certain names within VHDL description. These names could be among others, entity name, architecture name.

Ans: It is a code that generates the stimuli to test out design correctness. It automatically verifies the code accuracy. It also verifies whether the code meets the circuit requirements.

Ans: A buffer is an OUT port with read capability. A buffer port may have at most one driver within the architecture where as inout port is just bidirectional port.

Ans : A set of signals may also be declared as a signal array which is a concatenated set of signals.

Ans : < type> (< range>)

Ans : type array_name is array (index_range, index_range) of element_type; .

Ans : No we can declare the multi dimentional array as two uni dimentional array as shown in below example type byte is array (7 downto 0 ) of std_logic; type mem is array (3 downto 0) of byte;

Ans : in,out,inout,buffer.

Ans : “&”

Ans : Process having all inputs in sensitivity list..

Ans : Are identifiers with a fixed value.

Ans : it is the statement used to report an error when a condition i false.

Ans : assert < condition> report < message> severity< level>

Ans : Warning , Error , Failure.

Ans : Error.

Ans : both