Welcome to SystemVerilog

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

SystemVerilog provides a complete verification environment, employing Directed and Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve the verification process dramatically.

SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.